The next part of the PCB Design Flow Process starts on the layout until design completion for board fabrication.
15. PREPARE LAYOUT FOR TRACE ROUTING Compare Schematic CAE net list with the PCB Design net list using Netcheck Tools.
16. SETUP DESIGN RULES
Setup/Design Rules on “Default Clearance” rules and …
Setup/Design Rules on “Net Clearance” rules are to be set up for Voltage, Ground and Critical Nets.
Set class rules for high-speed technology.
17. MANUAL ROUTING
Manually Bus route memory sections using Copy/Paste command.
Manually fan out all Voltages that connect to an inner layer plane using Via Share technique.
Manually fan out all Ground connections so that every Ground Pin gets its own Via.
Manually route all other Voltages that require large trace widths.
Manually route all high-speed matched length traces and critical nets.
Use Tools/Verify Design/Check Planes to insure 100% fan out of all SMT Plane Pins.
Use Tools/Verify Design/Check Clearances to insure no short circuits.
If the design is a 2-Layer board, all voltages should be manually routed per Engineers specification.
18. Second (2nd) SET OF QUALITY PRINTS
PCB Designer will print all layers that were affected by manual routing and give them to the engineer.
If the placement or pad-stacks have changed run check prints of assembly & drill drawing
19. SIGNAL INTEGRITY OUTPUT
Generate a Hyperlynx file for signal analysis.
20. FIX ENGINEERS RED-LINED PRINTS
Incorporate all of the Project Engineers corrections
If there were many corrections, PCB Designer will create a new set of check prints.
21. TESTABILITY
The Project Engineer will be responsible for informing the PCB Designer the Testability Rules, early in the Process.
This includes the following questions:
Does every Net need a test point or just some of the nets?
Do voltage nets require extra test points?
Do non-connected pins need to be testable?
Will the Project Engineer add selective test points to the schematic?
Can vias be used as test points, or do they have to be “Bottom Side” non-drilled Pads?
What size do the test points have to be, what is the point to point spacing requirements & amount of pins per square inch?
Are there vacuum requirements for the test fixture?
If PCB Design requires testability on every net, the PCB Designer will add a test point for every net, using PADS DFT Audit program and place the test points, near one of the pins, of the net it belongs to.
22. ROUTE REMAINDER OF NON-CRITICAL ROUTES
If the PC Board has a large number of production boards made, it should be 100 % manually routed to reduce trace length, reduce via count and reduce layers.
If Project Engineer requested a quick turn proto-type, use an auto router to route remainder of board.
If auto routing is used, clean up the traces on all layers after the auto router has completed 100%
Make and save a pre-auto routed version of the PCB. This will be use for future revisions.
23. FINAL DRC CHECKS
PCB Designer & Project Engineer: Tools/Verify Design – Check Clearances, Continuity and Panes.
24. SILKSCREEN
Create Silkscreen (use 0.05mm snap grid) and bottom side etch text.
All reference designators must be moved outside component, and must not exceed two different rotations. All company identification & REV Blocks must be placed inside the board outline. Default text height/width is .080”/.008” Minimum height/width is .060”/.006”.
All connectors should have text to identify the end-pins. Add connector & jumper text names, if any.
25. Third (3rd) SET OF QUALITY PRINTS
Create check prints of all Routed Layers, Silk-screens, Solder Masks & Paste Masks.
Create check prints of final AutoCAD Drill & Assembly Drawings.
Check final CAE Netlist with final CAD Netlist.
26. FINAL CAM OUTPUT
Make final prints of AutoCAD Assembly & Drill Drawings.
Create Fabrication Data that contains Gerber Data, Drill Data & Fabrication Drawing.
Import the PADS ASCII file into CAM350 to extract an IPC-D-356 Netlist.
Create Assembly X/Y Coordinate Data.
Save all of the final output data to Source Safe.
